1. Field of the Invention
The invention relates to a method for isolation of a vertical DRAM, and more particularly to a method for improving DRAM quality by reversing the order of formation of a memory cell and isolation layer.
2. Description of the Related Art
Memory devices, such as Dynamic Random Access Memory (DRAM), for non-volatile storage of information, are currently in widespread use, in a myriad of applications.
A conventional DRAM consists of a transistor and a capacitor, with electric charges entering or leaving the capacitor during reading and writing. A deep trench capacitor is normally used to reduce the size of the memory device. The capacitor is disposed in the deep trench bottom, the transistor is disposed at the deep trench top, and a thick dielectric layer, such as trench top oxide (TTO) layer, acting as an electrical insulating layer, is disposed between the capacitor and the transistor.
FIGS. 1a to 1g are cross-sections of the conventional method for forming an isolation layer in a vertical DRAM. FIG. 3 is a top view of a vertical DRAM array, FIGS. 1e(a) to 1g(a) are cross-sections along line 11, and FIGS. 1e(b) to 1g(b) are cross-sections along line 22.
In FIG. 1a, a semiconductor substrate 100 is provided, on which a pad oxide layer 101, a pad nitride layer 102, and a patterned mask layer 400 with an opening 401 are formed, with the location of the opening 401 corresponding to a trench described subsequently. The pad oxide layer 101 and pad nitride layer 102 act as hard mask layers for etching the semiconductor substrate 100 to form a trench.
In FIG. 1b, the pad nitride layer 102 and the pad oxide layer are sequentially etched using the patterned mask layer 400 as an etching mask to form an opening, and the semiconductor substrate 100 is etched using the pad nitride layer 102 and the pad oxide layer 101 with the opening as etching masks to form a trench 100a. The trench 100a, deep in the semiconductor substrate 100, acts as a buried DRAM described in subsequent.
In FIG. 1c, a trench capacitor is disposed in the bottom portion of the trench 100a, comprising a buried plate, and a conformable capacitor dielectric layer and plate. A collar oxide layer 103 is formed on a sidewall of the trench 100a above the capacitor. A doped poly layer 104 is formed on the semiconductor substrate 100, and the trench 100a is filled, with the poly layer 104 acting as a capacitor wire.
In FIG. 1d, the poly layer 104 is etched to leave a poly layer 104a of a predetermined depth in the trench 100a. 
In FIG. 1e, the collar oxide layer 103 is recessed lower than the surface of the poly layer 104a to form a groove 105. A trench top oxide (TTO) layer 108 is formed on the poly 104a to isolate the trench capacitor and a gate described in subsequently. The semiconductor substrate 100 is annealed to diffuse the dopant from the poly layer 104a to the semiconductor substrate 100 via the groove 105, and thus an ion doped area 107 is formed in these semiconductor substrate 100. The ion doped area 107 acts as a buried strap to electrically connect the conducting layer 104a and the gate of the transistor, and acts as a drain of the transistor described in subsequently. A gate oxide 109 is conformably formed on a sidewall of the trench 100a, a poly layer lower than the surface of the pad nitride layer 102 is formed in the trench 100a, and another poly layer level with the pad nitride layer 102 is formed in the trench, completing poly layer 111 acting as the gate.
FIG. 1f(a) is a cross-section along line 11, and FIG. 1f(b) is a cross-section along line 22. A nitride layer 112, a borosilicate glass (BSG) layer 113, and a patterned photoresist layer 114 with a plurality of openings 115 are sequentially formed on the surface of the pad nitride layer 102 and the poly layer 111. The BSG layer 113 acts as a hard mask layer for forming a high quality trench, and the surface of the BSG layer 113 is exposed by the openings 115.
In FIGS. 1g(a) and 1g(b), the BSG layer 113 is etched using the patterned photoresist layer 114 to expose the nitride layer 112.
After the patterned photoresist layer 114 is removed, the nitride layer 112, the exposed pad nitride layer 102, the pad oxide layer 101, the exposed structures, and semiconductor substrate 100, are sequentially etched using the BSG layer 113 as an etching mask to form a deep trench in the semiconductor substrate 100.
Thermal oxidation is performed to form a liner oxide layer 116 on the exposed semiconductor substrate 100 in the trench, and a liner nitride layer 117 is conformably formed on the liner oxide layer 116. An oxide layer is formed on the nitride layer 112, and the trench is filled with oxide layer. The oxide layer is chemical mechanical polished (CMP) to expose the nitride layer 112, such that an isolation 118 is formed in the trench, and, the nitride layer is removed. The isolation layer 118 is thus complete, and an active area therebetween is defined.
However, the thermal oxidation forming the liner oxide layer 116 also subjects thermal energy on the ion doped area 107, such that the region of the ion doped area 107 is expanded to an ion doped area 107a, adjacent areas of which may overlap, such that the ion doped areas 107 are shortened.